HYB316400BTL-50 Datasheet - Siemens Semiconductor Group

HYB316400BTL-50 3.3V 4M x 4-Bit Dynamic RAM

DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns).

3.3V 4M x 4-Bit Dynamic RAM HYB3116400BJ/BT(L) -50/-60/-70 HYB3117400BJ/BT(L) -50/-60/-70 Advanced Information 4 194 304 words by 4-bit organization 0 to 70 °C operating temperature Performance: -50 tRAC tCAC tAA tRC tPC RAS access time CAS access time Access time from address Read/Write cycle time Fast page mode cycle time 50 13 25 90 35 -60 60 15 30 110 40 -70 70 20 35 130 45 ns ns ns ns ns .

HYB316400BTL-50 Features

* include single + 3.3 V (± 0.3 V) power supply, direct interfacing with high-performance logic device families.The HYB3116400BTL parts have a very low power „sleep mode“ supported by Self Refresh. Ordering Information Type HYB 3117400BJ-50 HYB 3117400BJ-60 HYB 3117400BJ-70 HYB 3117400BT-50 HYB 31174

HYB316400BTL-50 Datasheet (253.01 KB)