SI53360 Datasheet (Silicon Laboratories) - LVCMOS Fanout Clock Buffers

SI53360, LVCMOS Fanout Clock Buffers

4 2.1 LVCMOS Input Termination .

4 2.2 Input Mux .

4 2.3 Output Clock Termination Options .

Si53360/61/62/65 Data Sheet Low-Jitter, LVCMOS Fanout Clock Buffers with up to 12 outputs and Frequency Range from dc to 200 MHz The Si53360/61/62/65 family of LVCMOS fanout buffers is ideal for clock/data distribution and redundant clocking applications.

The family utilizes Silicon Labs advanced CMOS technology to fanout clocks from dc to 200 MHz with guaranteed low additive jitter, low skew, and low propagation delay variability.

Built-in LDOs deliver high PSRR performance and eliminates the

SI53360 Features

* Low additive jitter: 120 fs rms

* Built-in LDOs for high PSRR performance

* Up to 12 LVCMOS Outputs from LVCMOS inputs

* Frequency range: dc to 200 MHz

* Multiple configuration options

* Dual Bank option

* 2:1 Input MUX option

* RoHS