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UR5596 Datasheet - UTC

UR5596 DDR TERMINATION REGULATOR

The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme. The device contains a high-speed OP AMP to provide excellent .

UR5596 Features

* Source and sink current

* Low output voltage offset

* No external resistors required

* Linear topology

* Suspend To Ram (STR) functionality

* Low external component count

* Thermal shutdown protection CMOS IC www.unisonic.com.tw Copyright © 2022 Unisonic Technologies

UR5596_UTC.pdf

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Datasheet Details

Part number:

UR5596

Manufacturer:

UTC

File Size:

351.47 KB

Description:

Ddr termination regulator.

UR5596 Distributor

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UR5596 UR5596 DDR TERMINATION REGULATOR UTC