EDI88128CS - 128Kx8 Monolithic SRAM
I/O0-7 Data Inputs/Outputs A0-16 Address Inputs WE# Write Enable CS# Chip Select OE# Output Enable VCC Power (+5V ±10%) VSS Ground NC Not Connected BLOCK DIAGRAM Memory Array Address Buffer Address Decoder I/O Circuits I/O0-7 WE# CS# OE# White Electronic Designs Corp.
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EDI88128CS Features
* Access Times of 15
* , 17, 20, 25, 35, 45, 55ns
* CS# and OE# Functions for Bus Control
* 2V Data Retention (EDI88128LPS)
* TTL Compatible Inputs and Outputs
* Fully Static, No Clocks
* 32 pad Ceramic LCC (Package 141)
* 32 lead Ceramic Fl
