74ACT11112 - DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP
This device contains two independent J-K negative-edge-triggered flip-flops.
A low level at the PRE or CLR input sets or resets the outputs regardless of the levels of the other inputs.
When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferr
74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCAS064A D3339, JUNE 1989 REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Fully Buffered to Offer Maximum Isolation From External Disturbance Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise t EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Lat
