74SSTUB32865A - 28-BIT TO 56-BIT REGISTERED BUFFER

Description

This 28-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation.

One device per DIMM is required to drive up to stacked 18 SDRAM loads or two devices per DIMM are required to drive up to 36 stacked SDRAM loads.

1.
2 Member of the Texas Instruments Widebus+™ Family.
Pinout Optimizes DDR2 RDIMM PCB Layout.
1-to-2 Outputs Supports Stacked DDR2 RDIMMs.
High driver strength for heavily loaded DIMMs.
Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption.
Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line.
Supports SSTL_18 Data Inputs.
Differential Clock (CK and CK.

Texas Instruments

Part number	74SSTUB32865A
Manufacturer	Texas Instruments
File Size	767.64 KB
Description	28-BIT TO 56-BIT REGISTERED BUFFER
Datasheet	74SSTUB32865A Datasheet
Additional preview pages of the 74SSTUB32865A datasheet.

74S00 - QUAD 2-input NAND GATE (ETC)
74S04 - HEX INVERTING GATES (National Semiconductor)
74S08 - Quad 2-Input AND Gate (Fairchild Semiconductor)
74S08 - Quad 2-Input AND Gates (National Semiconductor)
74S08N - Quad 2-Input AND Gate (Fairchild Semiconductor)
74S10 - STTL type three 3-input NAND gate (TW)
74S112 - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop (Fairchild Semiconductor)
74S133 - 13-Input NAND Gate (SYC)
74S134 - 12-INPUT POSITIVE-NAND GATES (Fairchild)
74S134 - 12-INPUT POSITIVE-NAND GATES (Signetics)

Other Datasheets by Texas Instruments

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74SSTUB32865A www.ti.

Published: Dec 29, 2020 |