SN65LVDS94 - LVDS SERDES RECEIVER
The SN65LVDS94 LVDS serdes (serializer/deserializer) receiver contains four serial-in 7-bit parallel-out shift registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) line receivers in a single integrated circuit.
These functions allow receipt of synchronous data from a
SN65LVDS94 Features
* 4:28 Data Channel Expansion at up to 1.904 Gigabits per Second Throughput
* Suited for Point-to-Point Subsystem Communication With Very Low EMI
* 4 Data Channels and Clock Low-Voltage Differential Channels in and 28 Data and Clock Out Low-Voltage TTL Channels Out
