* a Class A (slow mode: AB) output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows the designer to optimize speed versus power dissipation. The settling time can be chosen by the control bits within the 16-bit data word. Implemented with a CMOS pr
TLV5613
318.22 KB
12-bit parallel digital-to-analog converter.
TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS174B DECEMBER 1997 REVISED NOVEMBER 2000 D.
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