74AHC257 Datasheet (nexperia) - Quad 2-input multiplexer

74AHC257, Quad 2-input multiplexer

The 74AHC257; 74AHCT257 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).

It is speciﬁed in compliance with JEDEC standard No.

7-A.

The 74AHC257; 74AHCT257 has four identical 2-input multiplexers with 3-state outputs, which select 4 bits of data from two

74AHC257 Features

* I Balanced propagation delays I All inputs have Schmitt-trigger actions I Non-inverting data path I Inputs accept voltages higher than VCC I Input levels: N For 74AHC257: CMOS level N For 74AHCT257: TTL level I ESD protection: N HBM EIA/JESD22-A114E exceeds 2000 V N MM EIA/JESD22-A115-A exceeds 200