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74HCT166-Q100 - 8-bit parallel-in/serial out shift register

This page provides the datasheet information for the 74HCT166-Q100, a member of the 74HC166-Q100 8-bit parallel-in/serial out shift register family.

Description

The 74HC166-Q100; 74HCT166-Q100 is an 8-bit serial or parallel-in/serial-out shift register.

Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1).
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C.
  • Wide supply voltage range from 2.0 V to 6.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Synchronous parallel-to-serial.

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Datasheet preview – 74HCT166-Q100

Datasheet Details

Part number 74HCT166-Q100
Manufacturer nexperia
File Size 273.00 KB
Description 8-bit parallel-in/serial out shift register
Datasheet download datasheet 74HCT166-Q100 Datasheet
Additional preview pages of the 74HCT166-Q100 datasheet.

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Full PDF Text Transcription

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74HC166-Q100; 74HCT166-Q100 8-bit parallel-in/serial out shift register Rev. 2 — 9 August 2021 Product data sheet 1. General description The 74HC166-Q100; 74HCT166-Q100 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and a serial output (Q7). When the parallel enable input (PE) is LOW, the data from D0 to D7 is loaded into the shift register on the next LOW-to-HIGH transition of the clock input (CP). When PE is HIGH, data enters the register serially at DS with each LOW-to-HIGH transition of CP. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of CP. A HIGH on CE disables the CP input.
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