AS7C251MFT18A Datasheet | Alliance Semiconductor Corporation

Features - - - - - - Organization: 1,048,576 words x18 bits Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow-through operation Asynchronous output enable control Available 100-pin TQFP package - - - - - Individual byte write and global write Multiple chip enables for easy expansion 2.5V core power supply Linear or interleaved burst control Snooze mode for reduced power-standby .. Logic block diagram CLK ADV ADSC ADSP A[19:0] CLK CS CLR Burst logic 20 18 20 Q D CS Address 1M x 18 Memory array 18 18 register GWE BWb BWE BWa CE0 CE1 CE2 D DQb CLK D DQa Q Byte Write registers Byte Write registers CLK D CE CLK D ZZ Enable register Output buffers Input registers Power down Enable delay register CLK OE DQ[a,b] Selection guide -75 Minimum cycle time Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 8.5 7.5 275 90 60 -85 10 8.5 250 80 60 -10 12 10 230 80 60 Units ns ns m A m A m A 12/24/04, v. 1.2 Alliance...