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AS7C251MFT36A - (AS7C251MFT32A / AS7C251MFT36A) 2.5V 1M x 32/36 Flow-through synchronous SRAM

Download the AS7C251MFT36A datasheet PDF. This datasheet also covers the AS7C251MFT32A variant, as both devices belong to the same (as7c251mft32a / as7c251mft36a) 2.5v 1m x 32/36 flow-through synchronous sram family and are provided as variant models within a single manufacturer datasheet.

General Description

The AS7C251MFT32A/36A is a high-performance CMOS 32-Mbit synchronous Static Random Access Memory (SRAM) device organized as 1,048,576 words × 32 or 36 bits.

Fast cycle times of 8.5/10/12 ns with clock access times (tCD) of 7.5/8.5/10 ns.

Three chip enable (CE) inputs permit easy memory expansion.

Key Features

  • Organization: 1,048,576 words × 32 or 36 bits Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow-through operation Asynchronous output enable control Available in 100-pin TQFP package Individual byte write and global write.
  • Multiple chip enables for easy expansion 2.5V core power supply Linear or interleaved burst control Snooze mode.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (AS7C251MFT32A_AllianceSemiconductorCorporation.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number AS7C251MFT36A
Manufacturer Alliance Semiconductor Corporation
File Size 566.64 KB
Description (AS7C251MFT32A / AS7C251MFT36A) 2.5V 1M x 32/36 Flow-through synchronous SRAM
Datasheet download datasheet AS7C251MFT36A Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
January 2005 ® AS7C251MFT32A AS7C251MFT36A 2.5V 1M × 32/36 Flow-through synchronous SRAM Features • • • • • • • Organization: 1,048,576 words × 32 or 36 bits Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow-through operation Asynchronous output enable control Available in 100-pin TQFP package Individual byte write and global write • • • • • Multiple chip enables for easy expansion 2.5V core power supply Linear or interleaved burst control Snooze mode for reduced power-standby Common data inputs and data outputs www.DataSheet4U.