AS7C331MNTD18A - 3.3V 1M x 18 Pipelined SRAM

Description

The AS7C331MNTD18A family is a high performance CMOS 16 Mbit synchronous Static Random Access Memory (SRAM) organized as 1,048,576 words × 18 bits and incorporates a LATE LATE Write.

Features

Organization: 1,048,576 words × 18 bits NTD™ architecture for efficient bus operation Fast clock speeds to 166 MHz Fast clock to data access: 3.4/3.8 ns Fast OE access time: 3.4/3.8 ns Fully synchronous operation Asynchronous output enable control Available in 100-pin TQFP package.
Individual byte write and global write Clock enable for op.

Alliance Semiconductor Corporation

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Datasheet Details

Part number	AS7C331MNTD18A
Manufacturer	Alliance Semiconductor Corporation
File Size	469.14 KB
Description	3.3V 1M x 18 Pipelined SRAM
Datasheet	AS7C331MNTD18A Datasheet
Additional preview pages of the AS7C331MNTD18A datasheet.

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Other Datasheets by Alliance Semiconductor Corporation

AS7C331MNTD32A - (AS7C331MNTD32A / AS7C331MNTD36A) 3.3V 1M x 32/36 Pipelined SRAM
AS7C331MNTD36A - (AS7C331MNTD32A / AS7C331MNTD36A) 3.3V 1M x 32/36 Pipelined SRAM
AS7C331MFT32A - (AS7C331MFT32A / AS7C331MFT36A) 3.3V 1M x 32/36 Flow-through synchronous SRAM
AS7C331MFT36A - (AS7C331MFT32A / AS7C331MFT36A) 3.3V 1M x 32/36 Flow-through synchronous SRAM
AS7C33128FT18B - 3.3V 128K x 18 Flow Through Synchronous SRAM
AS7C33128FT32B - (AS7C33128FT32B / AS7C33128FT36B) 3.3V 128K x 32/36 Flow Through Synchronous SRAM
AS7C33128FT36B - (AS7C33128FT32B / AS7C33128FT36B) 3.3V 128K x 32/36 Flow Through Synchronous SRAM
AS7C33128NTD18B - 3.3V 128Kx18 Pipelined SRAM

Full PDF Text Transcription

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December 2004 ® AS7C331MNTD18A 3.3V 1M x 18 Pipelined SRAM with NTDTM Features • • • • • • • • Organization: 1,048,576 words × 18 bits NTD™ architecture for efficient bus operation Fast clock speeds to 166 MHz Fast clock to data access: 3.4/3.8 ns Fast OE access time: 3.4/3.8 ns Fully synchronous operation Asynchronous output enable control Available in 100-pin TQFP package • • • • • • • • Individual byte write and global write Clock enable for operation hold Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Self-timed write cycles Interleaved or linear burst modes Snooze mode for standby operation www.DataSheet4U.

Published: Jan 1, 2009 |