Alliance Semiconductor Corporation AS7C331MNTD18A
The AS7C331MNTD18A family is a high performance CMOS 16 Mbit synchronous Static Random Access Memory (SRAM) organized as 1,048,576 words × 18 bits and incorporates a LATE LATE Write. This variation of the 16Mb+ synchronous SRAM uses the No Turnaround Delay (NTD™) architecture, featuring an enhanced write operation that improves bandwidth over pipelined burst devices. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modify-write operations.| Part No. | AS7C331MNTD18A |
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| Datasheet | AS7C331MNTD18A Download |
| Manufacturer |  Alliance Semiconductor Corporation |
| Description | 3.3V 1M x 18 Pipelined SRAM |
| Buy | Stock & Price |
FEATURES
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● Organization: 1,048,576 words × 18 bits NTD™ architecture for efficient bus operation Fast clock speeds to 166 MHz Fast clock to data access: 3.4/3.8 ns Fast OE access time: 3.4/3.8 ns Fully synchronous operation Asynchronous output enable control Available in 100-pin TQFP package
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● Individual byte write and global write Clock enable for operation hold Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Self-timed write cycles Interleaved or linear burst modes Snooze mode for standby operation Logic block diagram A[19:0] 20 D Address register burst logic Q 20 CLK CE0 CE1 CE2 R/W BWa BWb ADV / LD LBO ZZ 18 CLK D Q 20 Write delay addr. registers CLK Control logic CLK Write Buffer 1M x 18 SRAM array DQ [a,b] D Data Q input register CLK 18 18 18 18 CLK CEN CLK OE Output register 18 OE DQ [a,b] Selection guide -166 Minimum cycle time Maximum clock frequency Maximum clock access time Maximum oper...
