AS7C331MNTD36A Datasheet | Alliance Semiconductor Corporation

Features - Organization: 1,048,576 words × 32 or 36 bits - NTD™architecture for efficient bus operation - Fast clock speeds to 200 MHz - Fast clock to data access: 3.2/3.5/3.8 ns - Fast OE access time: 3.2/3.5/3.8 ns - Fully synchronous operation - Asynchronous output enable control .. - Available in 100-pin TQFP packages - Byte write enables Logic block diagram A[19:0] 20 D - Clock enable for operation hold - Multiple chip enables for easy expansion - 3.3V core power supply - 2.5V or 3.3V I/O operation with separate VDDQ - Self-timed write cycles - Interleaved or linear burst modes - Snooze mode for standby operation Address register Burst logic CLK CE0 CE1 CE2 R/W BWa BWb BWc BWd ADV / LD LBO ZZ 32/36 CLK Q 20 Write delay addr. registers Control logic Write Buffer 1M x 32/36 SRAM Array DQ[a,b,c,d] Data Q Input Register 32/36 32/36 32/36 32/36 CLK CEN CLK OE Output Register 32/36 OE DQ[a,b,c,d] Selection guide -200 Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current...