AS7C331MNTD32A - (AS7C331MNTD32A / AS7C331MNTD36A) 3.3V 1M x 32/36 Pipelined SRAM

Description

The AS7C331MNTD32A/36A family is a high performance CMOS 32 Mbit Synchronous Static Random Access Memory (SRAM) organized as 1,048,576 words × 32 or 36 bits and incorporates a LATE LATE Write.

Features

Organization: 1,048,576 words × 32 or 36 bits.
NTD™architecture for efficient bus operation.
Fast clock speeds to 200 MHz.
Fast clock to data access: 3.2/3.5/3.8 ns.
Fast OE access time: 3.2/3.5/3.8 ns.
Fully synchronous operation.
Asynchronous output enable control www. DataSheet4U. com.
Available in 100-pin TQFP packages.
Byte write enables Logic block diagram A[19:0] 20 D.
Clock enable for operation hold.

Alliance Semiconductor Corporation

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Datasheet Details

Part number	AS7C331MNTD32A
Manufacturer	Alliance Semiconductor Corporation
File Size	486.01 KB
Description	(AS7C331MNTD32A / AS7C331MNTD36A) 3.3V 1M x 32/36 Pipelined SRAM
Datasheet	AS7C331MNTD32A Datasheet
Additional preview pages of the AS7C331MNTD32A datasheet.

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Other Datasheets by Alliance Semiconductor Corporation

AS7C331MNTD36A - (AS7C331MNTD32A / AS7C331MNTD36A) 3.3V 1M x 32/36 Pipelined SRAM
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AS7C33128FT36B - (AS7C33128FT32B / AS7C33128FT36B) 3.3V 128K x 32/36 Flow Through Synchronous SRAM
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Full PDF Text Transcription

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December 2004 ® AS7C331MNTD32A AS7C331MNTD36A 3.3V 1M × 32/36 Pipelined SRAM with NTDTM Features • Organization: 1,048,576 words × 32 or 36 bits • NTD™architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.2/3.5/3.8 ns • Fast OE access time: 3.2/3.5/3.8 ns • Fully synchronous operation • Asynchronous output enable control www.DataSheet4U.com • Available in 100-pin TQFP packages • Byte write enables Logic block diagram A[19:0] 20 D • Clock enable for operation hold • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.

Published: Jan 1, 2009 |