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AS4LC4M4F1 Datasheet 4m X 4 CMOS Dram

Manufacturer: Alliance Semiconductor

Overview: .. May 2001 ® AS4LC4M4F1 4M×4 CMOS DRAM (Fast Page) 3.3V Family.

General Description

Address inputs Row address strobe Column address strobe Write enable Input/output Output enable Power Ground AS4LC4M4F1 *TSOP availability to be determined Selection guide Symbol Maximum RAS access time Maximum column address access time Maximum CAS access time Maximum output enable (OE) access time Minimum read or write cycle time Minimum fast page mode cycle time Maximum operating current Maximum CMOS standby current tRAC tCAA tCAC tOEA tRC tPC ICC1 ICC5 AS4LC4M4F1-50 50 25 12 13 80 25 120 1.0 AS4LC4M4F1-60 60 30 15 15 100 30 110 1.0 Unit ns ns ns ns ns ns mA mA 5/16/01;

v.1.0 Restored Alliance Semiconductor AS4LC4M4F1 P.

1 of 14 Copyright © Alliance Semiconductor.

Key Features

  • Organization: 4,194,304 words × 4 bits.
  • High speed - 50/60 ns RAS access time - 25/30 ns column address access time - 12/15 ns CAS access time.
  • Refresh - 2048 refresh cycles, 32 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh.
  • TTL-compatible, three-state I/O.
  • JEDEC standard package - 300 mil, 24/26-pin SOJ.
  • Low power consumption - Active: 500 mW max - Standby: 3.6 mW max, CMOS I/O.
  • Fast page mode.

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