AP2302 Datasheet | BCD Semiconductor

Preliminary Datasheet 3A DDR TERMINATION REGULATOR General Description The AP2302 linear regulator is designed to meet the JEDEC specification SSTL-2 and SSTL-18 for termination of DDR-SDRAM. The regulator can sink or source up to 3A current continuously, offers enough current for most DDR applications. Output voltage is designed to track the reference voltage within a 2% (DDR I) and 3% (DDR II) tolerance for load regulation while preventing shooting through on the output stage. On-chip thermal limiting provides protection against a bination of high current and ambient temperature which would create an excessive junction temperature. The AP2302, used in conjunction with series...