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AP2302 - 3A DDR TERMINATION REGULATOR

General Description

The AP2302 linear regulator is designed to meet the JEDEC specification SSTL-2 and SSTL-18 for termination of DDR-SDRAM.

The regulator can sink or source up to 3A current continuously, offers enough current for most DDR applications.

Key Features

  • Support Both DDR I (1.25VTT) and DDR II (0.9VTT) Requirements Source and Sink Current up to 3A High Accuracy Output Voltage at Full-load Adjustable VOUT by External Resistors Shutdown for Standby or Suspend Operation with High-impedance Output Mode.

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Datasheet Details

Part number AP2302
Manufacturer BCD Semiconductor
File Size 183.28 KB
Description 3A DDR TERMINATION REGULATOR
Datasheet download datasheet AP2302 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Preliminary Datasheet 3A DDR TERMINATION REGULATOR General Description The AP2302 linear regulator is designed to meet the JEDEC specification SSTL-2 and SSTL-18 for termination of DDR-SDRAM. The regulator can sink or source up to 3A current continuously, offers enough current for most DDR applications. Output voltage is designed to track the reference voltage within a 2% (DDR I) and 3% (DDR II) tolerance for load regulation while preventing shooting through on the output stage. On-chip thermal limiting provides protection against a combination of high current and ambient temperature which would create an excessive junction temperature.