CTL0343NS-R3 Datasheet | CT Micro

CTL0343NS-R3 N-Channel Enhancement MOSFET Features - Drain-Source Breakdown Voltage VDSS -20 V - Drain-Source On-Resistance RDS(ON) 58m, at VGS= 10V, ID= 3.4A RDS(ON) 66m, at VGS= 4.5V, ID= 2.7A RDS(ON) 88m, at VGS= 2.5V, ID= 1.0A - Continuous Drain Current at TC=25℃ID = -3.1A - Advanced high cell density Trench Technology - Ro HS pliance & Halogen Free Description The CTL0343NS-R3 is the N-Channel logic enhancement mode power field effect transistors are produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook puter power management and other battery powered circuits where low in-line power loss are needed in a very small outline surface mount package. Applications - Power Management - Lithium Ion Battery Package Outline Schematic Drain Gate Source Drain Gate Source CT Micro Proprietary & Confidential Page 1 Rev 1 Nov, 2013 CTL0343NS-R3 N-Channel Enhancement...