CTL0353PS-R3 Datasheet | CT Micro

CTL0353PS-R3 P-Channel Enhancement MOSFET Features - Drain-Source Breakdown Voltage VDSS -30 V - Drain-Source On-Resistance RDS(ON) 58m, at VGS= -10V, ID= -3.2A RDS(ON) 75m, at VGS= -4.5V, ID= -2.5A - Continuous Drain Current at TC=25℃ID = -3.0A - Advanced high cell density Trench Technology - Ro HS pliance & Halogen Free Applications - Power Management - Lithium Ion Battery Description The CTL0353PS-R3 is the P-Channel logic enhancement mode power field effect transistors are produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook puter power management and other battery powered circuits where low in-line power loss are needed in a very small outline surface mount package. Package Outline Schematic Drain Gate Source Drain Gate Source CT Micro Proprietary & Confidential Page 1 Rev 1 Nov, 2013 CTL0353PS-R3 P-Channel Enhancement...