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PROCESS
CP329V
Small Signal Transistor
NPN- Silicon Darlington Transistor Chip
PROCESS DETAILS Process Die Size Die Thickness Base Bonding Pad Area
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EPITAXIAL PLANAR 27 x 27 MILS 7.1 MILS 4.2 x 4.2 MILS 4.3 x 4.3 MILS Al Au - 30,000Å - 13,000Å
Emitter Bonding Pad Area Top Side Metalization Back Side Metalization GEOMETRY
GROSS DIE PER 4 INCH WAFER 15,980 PRINCIPAL DEVICE TYPES CMPTA29 CZTA29 MPSA29
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