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CY26049-36 - Global Communications Clock Generator

Datasheet Summary

Description

Reference Input Clock; 8 kHz or 10 to 60 MHz.

Clock Output; 8 kHz or high impedance in buffer mode.

Frequency Select 1; Determines CLK outputs per Table 1.

Features

  • Fully integrated phase-locked loop (PLL).
  • FailSafe output.
  • PLL driven by a crystal oscillator that is phase aligned with external reference.
  • Output frequencies selectable and/or programmed to standard communication frequencies.
  • Low-jitter, high-accuracy outputs.
  • Commercial and Industrial operation.
  • 3.3V ± 5% operation.
  • 16-lead TSSOP.
  • When reference is in range, SAFE pin is driven high.
  • When reference is.

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Datasheet Details

Part number CY26049-36
Manufacturer Cypress Semiconductor
File Size 1.01 MB
Description Global Communications Clock Generator
Datasheet download datasheet CY26049-36 Datasheet
Additional preview pages of the CY26049-36 datasheet.

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Full PDF Text Transcription

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CY26049-36 FailSafe™ PacketClock™ Global Communications Clock Generator Features • Fully integrated phase-locked loop (PLL) • FailSafe output • PLL driven by a crystal oscillator that is phase aligned with external reference • Output frequencies selectable and/or programmed to standard communication frequencies • Low-jitter, high-accuracy outputs • Commercial and Industrial operation • 3.3V ± 5% operation • 16-lead TSSOP • When reference is in range, SAFE pin is driven high. • When reference is off, DCXO maintains clock outputs. SAFE pin is low. • DCXO maintains continuous operation should the input reference clock fail • Glitch-free transition simplifies system design • Selectable output clock rates include T1/DS1, E1, T3/DS3, E3, and OC-3. • Works with commonly available, low-cost 18.
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