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CY26126 - Dual Output 125-MHz Clock Generator

General Description

Reference Input 3.3V Voltage Supply Output Enable Ground Ground 125-MHz Clock Output A 125-MHz Clock Output B Reference Output Absolute Maximum Conditions Parameter VDD TS TJ Storage Description Supply Voltage Temperature[2] Junction Temperature Digital Inputs Digital Outputs referred to VDD Electr

Key Features

  • Integrated phase-locked loop.
  • Low skew, low jitter, high accuracy outputs.
  • 3.3V Operation Part Number CY26126 Outputs 2 Input Frequency Range 25 MHz Output Frequencies 2 copies of 125 MHz (3.3V) Benefits Highest-performance PLL tailored for multimedia.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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5 Advance Information CY26126 Dual Output 125-MHz Clock Generator Features • Integrated phase-locked loop • Low skew, low jitter, high accuracy outputs • 3.3V Operation Part Number CY26126 Outputs 2 Input Frequency Range 25 MHz Output Frequencies 2 copies of 125 MHz (3.3V) Benefits Highest-performance PLL tailored for multimedia applications Meets critical timing requirements in complex system designs Logic Block Diagram 25 XIN XOUT P Comp OSC. Q VCO P OUTPUT MULTIPLEXER AND DIVIDERS 125 MHz 125 MHz PLL OE VDD VSS Pin Configurations CY26126 8-pin SOIC XIN VDD OE VSS 1 2 3 4 8 7 6 5 XOUT CLKB CLKA VSS www.DataSheet4U.com Cypress Semiconductor Corporation Document #: 38-07351 Rev.