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CY7C1387KV33 - 18-Mbit Pipelined DCD Sync SRAM

Download the CY7C1387KV33 datasheet PDF (CY7C1386KV33 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 18-mbit pipelined dcd sync sram.

Description

The CY7C1386KV33/CY7C1387KV33 SRAM integrates 512K

Features

  • Supports bus operation up to 200 MHz.
  • Available speed grades are 200, and 167 MHz.
  • Registered inputs and outputs for pipelined operation.
  • Optimal for performance (double-cycle deselect).
  • Depth expansion without wait state.
  • 3.3 V core power supply (VDD).
  • 2.5 V or 3.3 V I/O power supply (VDDQ).
  • Fast clock-to-output times.
  • 3 ns (for 200 MHz device).
  • Provides high performance 3-1-1-1 access rate.
  • User selectable burst counter supporting interle.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1386KV33-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Full PDF Text Transcription

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CY7C1386KV33 CY7C1387KV33 18-Mbit (512K × 36/1M × 18) Pipelined DCD Sync SRAM 18-Mbit (512K × 36/1M × 18) Pipelined DCD Sync SRAM Features ■ Supports bus operation up to 200 MHz ■ Available speed grades are 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ■ Depth expansion without wait state ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.
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