This page provides the datasheet information for the CY7C1645KV18, a member of the CY7C1643KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture family.
Datasheet Summary
Features
Separate independent read and write data ports.
Supports concurrent transactions.
450-MHz clock for high bandwidth.
Four-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces on both read and write ports
(data transferred at 900 MHz) at 450 MHz.
Available in 2.0-clock cycle latency.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high-speed
sys.
CY7C1612KV18- 144-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1613KV18- 144-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C1614KV18- 144-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1615KV18- 144-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C1618KV18- 144-Mbit DDR II SRAM Two-Word Burst Architecture
Full PDF Text Transcription
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CY7C1643KV18/CY7C1645KV18
144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)
144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)
Features
■ Separate independent read and write data ports ❐ Supports concurrent transactions
■ 450-MHz clock for high bandwidth ■ Four-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces on both read and write ports
(data transferred at 900 MHz) at 450 MHz ■ Available in 2.
CY7C1645KV18 Datasheet
