CY7C185 Datasheet | Cypress

1b CY 7C1 85 FOR REVIEW ONLY fax id: 1013 8K x 8 Static RAM Features - High speed - 15 ns - Fast t DOE - Low active power - 715 m W - Low standby power - 220 m W - CMOS for optimum speed/power - Easy memory expansion with CE1, CE2 and OE Features - TTL-patible inputs and outputs - Automatic power-down when deselected provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state drivers. This device has an automatic power-down feature (CE1 or CE2), reducing the power consumption by 70% when deselected. The CY7C185 is in a standard 300-mil-wide DIP and SOJ package. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A12). Reading the device is acplished by selecting the device and enabling the outputs, CE1 and OE active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. A die coat is used to insure alpha immunity. Functional Description The CY7C185 is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is Logic Block Diagram Pin Configurations DIP/SOJ Top View NC A4 A5 A6 A7 A8 A9 A10 A11 A12 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE CE2 A3 A2 A1 OE A0 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 C185- 2 I/O0 INPUT BUFFER I/O1 I/O2 I/O3 256 x 32 x 8 ARRA Y I/O4 I/O5 I/O6 CE1 CE2 WE OE C185- 1 A1 A2 A3 A4 A5 A6 A7 A8 COLUMN DECODER POWER DOWN I/O7 Selection Guide[1...