Datasheet4U.com

CY7C25682KV18

Manufacturer: Cypress (now Infineon)

CY7C25682KV18 datasheet preview

Datasheet Details

Part number	CY7C25682KV18
Datasheet	CY7C25682KV18-CypressSemiconductor.pdf
File Size	604.30 KB
Manufacturer	Cypress (now Infineon)
Description	72-Mbit DDR II+ SRAM Two-Word Burst Architecture

CY7C25682KV18 Overview

CY7C25682KV18 CY7C25702KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT.

CY7C25682KV18 Key Features

72-Mbit density (4M × 18, 2M × 36)
550 MHz clock for high bandwidth
Two-word burst for reducing address bus frequency
Double data rate (DDR) interfaces (data transferred at
Available in 2.5 clock cycle latency
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Echo Clocks (CQ and CQ) simplify data capture in high speed
Data valid pin (QVLD) to indicate valid data on the output
On-die termination (ODT) feature

More Datasheets from Cypress (now Infineon)

See all Cypress (now Infineon) datasheets

Part Number	Description
CY7C2561KV18	72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C2562XV18	72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
CY7C25632KV18	72-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C2563KV18	72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C2563XV18	72-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
CY7C2564XV18	72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
CY7C25652KV18	72-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C2565KV18	72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C2565XV18	72-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
CY7C25422KV18	72-Mbit QDR II+ SRAM Two-Word Burst Architecture

CY7C25682KV18 Distributor