CY7C25682KV18 Overview
CY7C25682KV18 CY7C25702KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT.
CY7C25682KV18 Key Features
- 72-Mbit density (4M × 18, 2M × 36)
- 550 MHz clock for high bandwidth
- Two-word burst for reducing address bus frequency
- Double data rate (DDR) interfaces (data transferred at
- Available in 2.5 clock cycle latency
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Echo Clocks (CQ and CQ) simplify data capture in high speed
- Data valid pin (QVLD) to indicate valid data on the output
- On-die termination (ODT) feature