CYRS1542AV18 Description
The CYRS1542AV18 and CYRS1544AV18 are synchronous pipelined SRAMs, equipped with 1.8-V QDR II+ architecture with RadStop™ technology. Cypress’s state-of-the-art RadStop Technology is radiation hardened through proprietary design and process hardening techniques. The QDR II+ architecture has separate data inputs and data outputs to pletely eliminate the need to turnaround the data bus that exists with mon I/O devices.
CYRS1542AV18 Key Features
- Separate independent read and write data ports
- Supports concurrent transactions
- 250-MHz clock for high bandwidth
- 2-word burst on all accesses
- Double data rate (DDR) interfaces on both read and write ports at 250 MHz (data transferred at 500 MHz)
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Echo clocks (CQ and CQ) simplify data capture in high speed systems
- Single multiplexed address input bus latches address inputs for both read and write ports
- Separate port selects for depth expansion