CY62146G-MoBL Datasheet | Cypress

CY62146G Mo BL® Automotive 4-Mbit (256K words × 16 bit) Static RAM with Error-Correcting Code (ECC) 4-Mbit (256K words × 16 bit) Static RAM with Error-Correcting Code (ECC) Features - AEC-Q100 qualified - High speed: 45 ns - Temperature Range - Automotive-A: -40 C to +85 C - Ultra-low standby power - Typical standby current: 3.5 A - Embedded ECC for single-bit error correction[1] - Voltage range: 2.2 V to 3.6 V, 4.5 V to 5.5 V - 1.0-V data retention - TTL-patible inputs and outputs - Pb-free 44-pin TSOP II package Functional Description CY62146G is high-performance CMOS low-power (Mo BL) SRAM devices with embedded ECC. Device is accessed by asserting the chip enable (CE) input LOW. Data writes are performed by asserting the Write Enable (WE) input LOW, while providing the data on I/O0 through I/O15 and address on A0 through A17 pins. The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs control write operations to the upper and lower bytes of the specified memory location. BHE controls I/O8 through I/O15 and BLE controls I/O0 through I/O7. Data reads are performed by asserting the Output Enable (OE) input and providing the required address on the address lines. Read data is accessible on the I/O lines (I/O0 through I/O15). Byte accesses can be performed by asserting the required byte enable signal (BHE or BLE) to read either the upper byte or the lower byte of data from the specified address location. All I/Os (I/O0 through I/O15) are placed in a HI-Z state when the device is deselected (CE HIGH), or control signals are de-asserted (OE, BLE, BHE). The logic block diagram is on page 2. Product Portfolio Product CY62146G30 CY62146G Power Dissipation Features and Options (see Pin Configuration - CY62146G on page 4) Range VCC Range (V) Speed (ns) Operating ICC (m A) f = fmax Standby, ISB2 (µA) Typ[2] Max...