CY7C1352 Description
The CY7C1352 is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352 is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle.
CY7C1352 Key Features
- Pin patible and functionally equivalent to ZBT™ devices MCM63Z818 and MT55L256L18P
- Supports 143-MHz bus operations with zero wait states
- Data is transferred on every clock
- Internally self-timed output buffer control to eliminate the need to use OE
- Fully registered (inputs and outputs) for pipelined operation
- Byte Write Capability
- 256K x 18 mon I/O architecture
- Single 3.3V power supply
- Fast clock-to-output times
- 4.0 ns (for 143-MHz device)