CY7C1352G Description
The CY7C1352G is a 3.3 V, 256K × 18 synchronous-pipelined burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1352G is equipped.
CY7C1352G Key Features
- Pin patible and functionally equivalent to ZBT™ devices
- Internally self-timed output buffer control to eliminate the need
- Byte write capability
- 256K × 18 mon I/O architecture
- 3.3 V core power supply (VDD)
- 2.5 V/3.3 V I/O power supply (VDDQ)
- Fast clock-to-output times
- 4.0 ns (for 133-MHz device)
- Clock enable (CEN) pin to suspend operation
- Synchronous self-timed writes