Description
PIN
clk rst en adatai[31:0] bdatai[31:0] gto eqo lto ifo
TYPE
Input Input Input Input Input
DESCRIPTION
Global system clock Global system reset Enable computing A data bus input B data bus input
output A>B output output A=B output output A
Features
- Full IEEE-754 compliance Single precision real format support Simple interface No programming required 1 level pipeline Results available at every clock Fully configurable Fully synthesizable, static synchronous design with no internal tri-states
Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support.
DFPCOMP Datasheet
