DFPCOMP Description
Floating Point parator Unit ver 2.10 OVERVIEW DELIVERABLES ♦ Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment ◊ Active-HDL automatic simulation macros ◊ NCSim automatic simulation macros ◊ ModelSim automatic simulation macros ◊ Tests with reference responses Technical documentation ◊ ◊ ◊ The DFPP pares two arguments. The input...
DFPCOMP Key Features
- Full IEEE-754 pliance Single precision real format support Simple interface No programming required 1 level pipeline Res
- Digital Core Design. All Rights Reserved
- Upgrade from
- performs input data analyze against IEEE-754 number standard pliance. The appropriate numbers and information about the
- performs floating point pare function. Gives the plex information about the results and makes final flags settings