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DFPCOMP Datasheet Floating Point Comparator Unit

Manufacturer: Digital Core Design

Overview: DFPP .. Floating Point parator Unit ver 2.10 OVERVIEW DELIVERABLES ♦ Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment ◊ Active-HDL automatic simulation macros ◊ NCSim automatic simulation macros ◊ ModelSim automatic simulation macros ◊ Tests with reference responses Technical documentation ◊ ◊ ◊ The DFPP pares two arguments. The input numbers format is according to IEEE-754 standard. DFPP supports single precision real numbers. pare operation was pipelined up to 1 level. Input data are fed every clock cycle. The first result appears after 1 clock period latency and next results are available each clock cycle. Full IEEE-754 unordered pare function is included.

Datasheet Details

Part number DFPCOMP
Manufacturer Digital Core Design
File Size 170.88 KB
Description Floating Point Comparator Unit
Datasheet DFPCOMP_DigitalCoreDesign.pdf

Key Features

  • Full IEEE-754 compliance Single precision real format support Simple interface No programming required 1 level pipeline Results available at every clock Fully configurable Fully synthesizable, static synchronous design with no internal tri-states Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support.

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