DFPMUL Description
Floating Point Pipelined Multiplier Unit ver 2.70 OVERVIEW Fully synthesizable, static synchronous design with no internal tri-states The DFPMUL uses the pipelined mathematics algorithm to multiply two arguments. The input numbers format is according to IEEE754 standard. DFPMUL supports single precision real number.
DFPMUL Key Features
- Full IEEE-754 pliance Single precision real format support Simple interface No programming required 7 levels pipeline Fu
- Digital Core Design. All Rights Reserved
- performs input data analyze against IEEE-754 number standard pliance. The appropriate numbers and information about the
- performs floating point multiply f