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DFPDIV Datasheet Floating Point Pipelined Divider Unit

Manufacturer: Digital Core Design

Overview: DFPDIV .. Floating Point Pipelined Divider Unit ver 2.15 OVERVIEW ● Fully synthesizable, static synchronous design with no internal tri-states The DFPDIV uses the pipelined mathematics algorithm to divide two arguments. The input numbers format is according to IEEE754 standard. DFPDIV supports single precision real number. Divide operation was pipelined up to 15 levels. Input data are fed every clock cycle. The first result appears after 15 clock periods latency and next results are available each clock cycle. Full IEEE-754 precision and accuracy are included.

Datasheet Details

Part number DFPDIV
Manufacturer Digital Core Design
File Size 170.53 KB
Description Floating Point Pipelined Divider Unit
Datasheet DFPDIV_DigitalCoreDesign.pdf

Key Features

  • Full IEEE-754 compliance Single precision real format support Simple interface No programming required 15 levels pipeline Full accuracy and precision Results available at every clock Overflow, underflow and invalid operation flags Fully configurable Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support.

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