Digital Core Design DFPDIV
The DFPDIV uses the pipelined mathematics algorithm to divide two arguments. The input numbers format is according to IEEE754 standard. DFPDIV supports single precision real number.| Part No. | DFPDIV |
|---|---|
| Datasheet | DFPDIV Download |
| Manufacturer |  Digital Core Design |
| Description | Floating Point Pipelined Divider Unit |
| Buy | Stock & Price |
FEATURES
●●
●
●
●
●
●
●
● Full IEEE-754 compliance Single precision real format support Simple interface No programming required 15 levels pipeline Full accuracy and precision Results available at every clock Overflow, underflow and invalid operation flags Fully configurable Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support LICENSING Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows using IP Core in single FPGA bitstream and ASIC implemenhttp:// All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. tation. It also permits FPGA prototyping before ASIC production. Unlimited Designs license allows using IP Core in unlimited number of FPGA bitstreams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited.
