F59L2G81KA-25BG2N Description
The device has two 2176-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2176-byte increments. The Erase operation is implemented in a single block unit (128Kbytes + 8Kbytes). The device is a memory device which utilizes the I/O pins for both address and data input/output as well as mand inputs.
F59L2G81KA-25BG2N Key Features
- Voltage Supply VCC: 3.3V (2.7 V ~ 3.6V)
- Organization Page Size: (2K + 128) bytes Data Register: (2K + 128) bytes Block Size: 64Pages = (128K + 8K) bytes
- Automatic Program and Erase Page Program: (2K + 128) bytes Block Erase: (128K + 8K) bytes
- Page Read Operation Random Read: 25us (Max.) Read Cycle: 25ns
- Write Cycle Time Page Program Time: 400us (Typ.) 700us (Max.) Block Erase Time: 3 ms (Typ.) 10ms (Max.)
- 1bit/cell
- mand/Address/Data Multiplexed DQ Port
- Hardware Data Protection
- Reliable CMOS Floating Gate Technology
- mand Register Operation