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F59L2G81KA-25TG2N - 2-Gbit 3.3V NAND Flash Memory

Download the F59L2G81KA-25TG2N datasheet PDF. This datasheet also covers the F59L2G81KA variant, as both devices belong to the same 2-gbit 3.3v nand flash memory family and are provided as variant models within a single manufacturer datasheet.

General Description

The device has two 2176-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2176-byte increments.

The Erase operation is implemented in a single block unit (128Kbytes + 8Kbytes).

Key Features

  • Voltage Supply ­ VCC: 3.3V (2.7 V ~ 3.6V).
  • Organization ­ Page Size: (2K + 128) bytes ­ Data Register: (2K + 128) bytes ­ Block Size: 64Pages = (128K + 8K) bytes ­ Number of Block per Die (LUN)= 2048.
  • Automatic Program and Erase ­ Page Program: (2K + 128) bytes ­ Block Erase: (128K + 8K) bytes.
  • Page Read Operation ­ Random Read: 25us (Max. ) ­ Read Cycle: 25ns.
  • Write Cycle Time ­ Page Program Time: 400us (Typ. ) 700us (Max. ) ­ Block Erase Time: 3 ms (Typ. ) 10ms (Max. ) F5.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (F59L2G81KA-ESMT.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ESMT Flash FEATURES  Voltage Supply ­ VCC: 3.3V (2.7 V ~ 3.6V)  Organization ­ Page Size: (2K + 128) bytes ­ Data Register: (2K + 128) bytes ­ Block Size: 64Pages = (128K + 8K) bytes ­ Number of Block per Die (LUN)= 2048  Automatic Program and Erase ­ Page Program: (2K + 128) bytes ­ Block Erase: (128K + 8K) bytes  Page Read Operation ­ Random Read: 25us (Max.) ­ Read Cycle: 25ns  Write Cycle Time ­ Page Program Time: 400us (Typ.) 700us (Max.) ­ Block Erase Time: 3 ms (Typ.) 10ms (Max.) F59L2G81KA (2N) Operation Temperature Condition -40°C~105°C 2 Gbit (256M x 8) 3.