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M12L128168A-6TVAG2N Datasheet Synchronous DRAM

Manufacturer: ESMT (Elite Semiconductor Microelectronics Technology)

Overview: ESMT SDRAM.

Download the M12L128168A-6TVAG2N datasheet PDF. This datasheet also includes the M12L128168A-5TVG2N variant, as both parts are published together in a single manufacturer document.

General Description

The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits.

Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.

Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Key Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst Read single write operation.
  • DQM for masking.
  • Auto & self refresh (self refresh is not supported for VA grade).
  • Refresh - 64ms refresh.