M53D128324A - Mobile DDR SDRAM

Product Overview

ESMT

Part number	M53D128324A
Manufacturer	ESMT
File Size	1.22 MB
Description	Mobile DDR SDRAM
Datasheet	M53D128324A Datasheet
Additional preview pages of the M53D128324A datasheet.

JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) No DLL; CLK to DQS is not synchronized. Differential clock inputs (CLK and CLK ) Four bank operation CAS Latency : 2, 3 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8, 16 Special function support - PASR (Partial Array Self Refresh) - Internal TCSR (Temperature Compensated Self Refresh) - DS (Drive Strength) M53D128324A (2E) 1M x 32 Bit x 4 Banks Mobile.

📁 Similar Datasheet

Other Datasheets by ESMT

Published: Sep 20, 2018 |