M53D256328A Overview
Ball Name Function A0~A11, BA0~BA1 Address inputs - Row address A0~A11 - Column address A0~A8 A10/AP : Bank selects (4 Banks) DQ0~DQ31 Data-in/Data-out RAS CAS WE VSS VDD DQS0~DQS3 Row address strobe Column address strobe Write enable Ground Power Bi-directional Data Strobe. DQS0 corresponds to the data on DQ0~DQ7;.
M53D256328A Key Features
- JEDEC Standard
- Internal pipelined double-data-rate architecture, two data
- Bi-directional data strobe (DQS)
- No DLL; CLK to DQS is not synchronized
- Differential clock inputs (CLK and CLK )
- Four bank operation
- CAS Latency : 3
- Burst Type : Sequential and Interleave
- Burst Length : 2, 4, 8, 16
- Special function support