Click to expand full text
ESMT
M56Z8G32256A
LPDDR4/LPDDR4X SDRAM
32M x 32 Bit x 8 Banks LPDDR4/LPDDR4X SDRAM
Feature
Ultra-low-voltage core and I/O power supply – VDD1 = 1.70–1.95V; 1.80V nominal – VDD2 = 1.06–1.17V; 1.10V nominal – VDDQ = 1.06–1.17V; 1.10V nominal or Low VDDQ = 0.57–0.65V; 0.60V nominal
Array configuration – 256 Meg × 32 (2 channels ×16 I/O)
Device configuration – 256M16 × 2 die in package
16n prefetch DDR architecture 8 internal banks per channel for concurrent operation Single-data-rate CMD/ADR entry Bidirectional/differential data strobe per byte lane Programmable READ and WRITE latencies (RL/WL) Programmable and on-the-fly burst lengths (BL = 16, 32) Directed per-bank refresh for concurrent bank operation and ease of command scheduling Up to 8.
M56Z8G32256A Datasheet
