P4C1024 Datasheet | Unknown Manufacturer

FEATURES High Speed (Equal Access and Cycle Times) - 15/17/20/25/35 ns (mercial) - 20/25/35/45 ns (Industrial) Single 5 Volts ±10% Power Supply Easy Memory Expansion Using CE1, CE2 and OE Inputs mon Data I/O Three-State Outputs Fully TTL patible Inputs and Outputs Advanced CMOS Technology Fast t OE Automatic Power Down Packages - 32-Pin 300 mil DIP and SOJ - 32-Pin 400 mil SOJ DESCRIPTION The P4C1024 is a 1,048,576-bit high-speed CMOS static RAM organized as 128Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-patible. The RAM operates from a single 5V±10% tolerance power supply. The P4C1024 device provides asynchronous operations with matching access and cycle times. Memory locations are specified on address pins A0 to A16. Reading is acplished by device selection (CE1 low and CE2 high) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory Access times of 15 nanoseconds permit greatly en- location is presented on the data input/output pins. The hanced system operating speeds. CMOS is utilized to input/output pins stay in the HIGH Z state when either reduce power consumption to a low level. The P4C1024 CE1 or OE is HIGH or WE or CE2 is LOW. is a member of a family of PACE RAM™ products offering fast access times. Package options for the P4C1024 include 32-pin 300 mil DIP and SOJ packages as well as 400 mil SOJ. FUNCTIONAL BLOCK DIAGRAM ROW SELECT - - - PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 (9) A 262,144BIT MEMORY ARRAY A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 I/O1 - - - - - - - - - - - - - - - - - - INPUT DATA CONTROL COLUMN I/O I/O2 COLUMN SELECT WE CE1 CE2 OE CONTROL CIRCUIT A - - - - - -...