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M24L416256DA - 4-Mbit (256K x 16) Pseudo Static RAM

General Description

of read and write modes.

The M24L416256DA is a high-performance CMOS pseudo static RAM (PSRAM) organized as 256K words by 16 bits that supports an asynchronous memory interface.

Key Features

  • Advanced low-power architecture.
  • High speed: 55 ns, 60 ns and 70 ns.
  • Wide voltage range: 2.7V to 3.6V.
  • Typical active current: 1 mA @ f = 1 MHz.
  • Low standby power.
  • Automatic power-down when deselected www. DataSheet4U. com M24L416256DA 4-Mbit (256K x 16) Pseudo Static RAM reducing power consumption dramatically when deselected ( CE1 HIGH, CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-imped.

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Datasheet Details

Part number M24L416256DA
Manufacturer Elite Semiconductor Memory Technology
File Size 346.71 KB
Description 4-Mbit (256K x 16) Pseudo Static RAM
Datasheet download datasheet M24L416256DA Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ESMT PSRAM Features • Advanced low-power architecture •High speed: 55 ns, 60 ns and 70 ns •Wide voltage range: 2.7V to 3.6V •Typical active current: 1 mA @ f = 1 MHz •Low standby power •Automatic power-down when deselected www.DataSheet4U.com M24L416256DA 4-Mbit (256K x 16) Pseudo Static RAM reducing power consumption dramatically when deselected ( CE1 HIGH, CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected ( CE1 HIGH, CE2 LOW, OE is HIGH), or during a write operation (Chip Enabled and Write Enable WE LOW). Reading from the device is accomplished by asserting the Chip Enables ( CE1 LOW and CE2 HIGH) and Output Enable( OE ) LOW while forcing the Write Enable ( WE ) HIGH.