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M24L416256SA - 4-Mbit (256K x 16) Pseudo Static RAM

General Description

of read and write modes.

The M24L416256SA is a high-performance CMOS Pseudo static RAM organized as 256K words by 16 bits that supports an asynchronous memory interface.

Key Features

  • Wide voltage range: 2.7V.
  • 3.6V.
  • Access time: 55 ns, 60 ns and 70 ns.
  • Ultra-low active power.
  • Typical active current: 1 mA @ f = 1 MHz.
  • Typical active current: 8 mA @ f = fmax (70-ns speed).
  • Ultra low standby power.
  • Automatic power-down when deselected.
  • CMOS for optimum speed/power www. DataSheet4U. com M24L416256SA 4-Mbit (256K x 16) Pseudo Static RAM The input/output pins (I/O0through I/O15) are placed in a high-imp.

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Datasheet Details

Part number M24L416256SA
Manufacturer Elite Semiconductor Memory Technology
File Size 350.64 KB
Description 4-Mbit (256K x 16) Pseudo Static RAM
Datasheet download datasheet M24L416256SA Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ESMT PSRAM Features • Wide voltage range: 2.7V–3.6V • Access time: 55 ns, 60 ns and 70 ns • Ultra-low active power — Typical active current: 1 mA @ f = 1 MHz — Typical active current: 8 mA @ f = fmax (70-ns speed) • Ultra low standby power • Automatic power-down when deselected • CMOS for optimum speed/power www.DataSheet4U.com M24L416256SA 4-Mbit (256K x 16) Pseudo Static RAM The input/output pins (I/O0through I/O15) are placed in a high-impedance state when : deselected ( CE HIGH), outputs are disabled ( OE HIGH), both Byte High Enable and Byte Low Enable are disabled ( BHE , BLE HIGH), or during a write operation ( CE LOW and WE LOW). Writing to the device is accomplished by taking Chip Enable( CE LOW) and Write Enable ( WE ) input LOW.