EDD1232AABH Description
The EDD1232AABH is a 128M bits DDR SDRAM organized as 1,048,576 words × 32 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture.
EDD1232AABH Key Features
- Power supply: VDDQ = 2.5V ± 0.2V : VDD = 2.5V ± 0.2V
- Data rate: 333Mbps/266Mbps (max.)
- Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver
- Data inputs, outputs, and DM are synchronized with DQS
- 4 internal banks for concurrent operation
- DQS is