EDD1208ALTA Description
The synchronous DRAMs use Double Data Rate (DDR) where data bandwidth is twice of regular synchronous DRAM. The synchronous DRAM is patible with SSTL_2 (Stub Series terminated Logic for 2.5 V). The synchronous DRAM is packaged in 66-pin Plastic TSOP (II).
EDD1208ALTA Key Features
- Fully Synchronous Dynamic RAM with all input signals except DM, DQS and DQ referenced to a positive clock edge
- Double Data Rate interface
- Quad internal banks operation
- Possible to a