EDD1208ALTA - 128 M-bit Synchronous DRAM

This page provides the datasheet information for the EDD1208ALTA, a member of the EDD1204ALTA 128 M-bit Synchronous DRAM family.

Description

random-access memories, organized as 8,388,608x4x4, 4,194,304x8x4, 2,097,152x16x4 (word x bit x bank), respectively.

Features

Fully Synchronous Dynamic RAM with all input signals except DM, DQS and DQ referenced to a positive clock edge.
Double Data Rate interface Differential CLK (/CLK) input Data inputs and DM are synchronized with both edges of DQS Data outputs and DQS are synchronized with a cross point of CLK and /CLK.
Quad internal banks operation.
Possible to a.

Elpida Memory

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Datasheet Details

Part number	EDD1208ALTA
Manufacturer	Elpida Memory
File Size	1.60 MB
Description	128 M-bit Synchronous DRAM
Datasheet	EDD1208ALTA Datasheet
Additional preview pages of the EDD1208ALTA datasheet.

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Full PDF Text Transcription

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PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 128 M-bit Synchronous DRAM with Double Data Rate (4-bank, SSTL_2) Description The EDD1204ALTA, EDD1208ALTA, EDD1216ALTA are high-speed 134,217,728 bits synchronous dynamic random-access memories, organized as 8,388,608x4x4, 4,194,304x8x4, 2,097,152x16x4 (word x bit x bank), respectively. The synchronous DRAMs use Double Data Rate (DDR) where data bandwidth is twice of regular synchronous DRAM. The synchronous DRAM is compatible with SSTL_2 (Stub Series terminated Logic for 2.5 V). The synchronous DRAM is packaged in 66-pin Plastic TSOP (II).

Published: Feb 6, 2017 |