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EDD1216AASE - 128M bits DDR SDRAM

Description

The EDD1216AASE is a 128M bits Double Data Rate (DDR) SDRAM organized as 2,097,154 words × 16 bits × 4 banks.

Read and write operations are performed at the cross points of the CK and the /CK.

This highspeed data transfer is realized by the 2 bits prefetchpipelined architecture.

Features

  • Power supply : VDDQ = 2.5V ± 0.2V : VDD = 2.5V ± 0.2V.
  • Data rate: 333Mbps/266Mbps (max. ).
  • Double Data Rate architecture; two data transfers per clock cycle.
  • Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver.
  • Data inputs, outputs, and DM are synchronized with DQS.
  • 4 internal ban.

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Datasheet preview – EDD1216AASE

Datasheet Details

Part number EDD1216AASE
Manufacturer Elpida Memory
File Size 557.48 KB
Description 128M bits DDR SDRAM
Datasheet download datasheet EDD1216AASE Datasheet
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Full PDF Text Transcription

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PRELIMINARY DATA SHEET 128M bits DDR SDRAM EDD1216AASE (8M words × 16 bits) Description The EDD1216AASE is a 128M bits Double Data Rate (DDR) SDRAM organized as 2,097,154 words × 16 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 2 bits prefetchpipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. It is packaged in 60-ball FBGA (µBGA) package. Features • Power supply : VDDQ = 2.5V ± 0.2V : VDD = 2.5V ± 0.2V • Data rate: 333Mbps/266Mbps (max.
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