EDD1216AATA - 128M bits DDR SDRAM

Description

The EDD1216AATA is a 128M bits Double Data Rate (DDR) SDRAM organized as 2,097,154 words × 16 bits × 4 banks.

Read and write operations are performed at the cross points of the CK and the /CK.

This highspeed data transfer is realized by the 2 bits prefetchpipelined architecture.

Features

Power supply : VDD ,VDDQ = 2.5V ± 0.2V.
Data rate: 333Mbps/266Mbps (max. ).
Double Data Rate architecture; two data transfers per clock cycle.
Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver.
Data inputs, outputs, and DM are synchronized with DQS.
4 internal banks for concurrent operation.
DQS.

Elpida Memory

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Datasheet Details

Part number	EDD1216AATA
Manufacturer	Elpida Memory
File Size	544.41 KB
Description	128M bits DDR SDRAM
Datasheet	EDD1216AATA Datasheet
Additional preview pages of the EDD1216AATA datasheet.

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Full PDF Text Transcription

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DATA SHEET 128M bits DDR SDRAM EDD1216AATA (8M words × 16 bits) Description The EDD1216AATA is a 128M bits Double Data Rate (DDR) SDRAM organized as 2,097,154 words × 16 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 2 bits prefetchpipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. It is packaged in 66-pin plastic TSOP (II). Features • Power supply : VDD ,VDDQ = 2.5V ± 0.2V • Data rate: 333Mbps/266Mbps (max.

Published: Feb 6, 2017 |