EDD1232ABBH - 128M bits DDR SDRAM

Features

×32 organization.
Double-data-rate architecture; two data transfers per clock cycle.
The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture.
Bi-directional data strobe (DQS) is trans.

Elpida Memory

Datasheet Details

Part number	EDD1232ABBH
Manufacturer	Elpida Memory
File Size	515.23 KB
Description	128M bits DDR SDRAM
Datasheet	EDD1232ABBH Datasheet
Additional preview pages of the EDD1232ABBH datasheet.

📁 Similar Datasheet

EDD11 - Doppelendtriode (TELEFUNKEN)

Other Datasheets by Elpida Memory

EDD1232AABH - 128M bits DDR SDRAM
EDD1232AAFA - 128M bits DDR SDRAM
EDD12322GBH-TS - 128M bits DDR Mobile RAM
EDD1204ALTA - 128 M-bit Synchronous DRAM
EDD1208ALTA - 128 M-bit Synchronous DRAM
EDD1216AASE - 128M bits DDR SDRAM
EDD1216AATA - 128M bits DDR SDRAM
EDD1216ALTA - 128 M-bit Synchronous DRAM

Full PDF Text Transcription

Click to expand full text

DATA SHEET 128M bits DDR SDRAM EDD1232ABBH (4M words × 32 bits) Specifications • Density: 128M bits • Organization ⎯ 1M words × 32 bits × 4 banks • Package: 144-ball FBGA ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 2.5V ± 0.125V • Data rate: 400Mbps (max.) • Four internal banks for concurrent operation • Interface: SSTL_2 • Burst lengths (BL): 2, 4, 8 • Burst type (BT): ⎯ Sequential (2, 4, 8) ⎯ Interleave (2, 4, 8) • /CAS Latency (CL): 3 • Precharge: auto precharge operation for each burst access • Driver strength: weak/matched • Refresh: auto-refresh, self-refresh • Refresh cycles: 4096 cycles/32ms ⎯ Average refresh period: 7.

Published: Feb 6, 2017 |