EDD5116ADTA-E Datasheet | Elpida Memory

Description The EDD5104AD, the EDD5108AD and the EDD5116AD are 512M bits Double Data Rate (DDR) SDRAM. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 2 bits prefetchpipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. It is packaged in standard 66-pin plastic TSOP (II). Pin Configurations /xxx indicates active low signal. 66-pin Plastic TSOP(II) VDD VDD VDD NC DQ0 DQ0 VDDQ VDDQ VDDQ NC NC DQ1 DQ0 DQ1 DQ2 VSSQ VSSQ VSSQ NC NC DQ3 NC DQ2 DQ4 VDDQ VDDQ VDDQ NC NC DQ5 DQ1 DQ3 DQ6 VSSQ VSSQ VSSQ NC NC DQ7 NC NC NC VDDQ VDDQ VDDQ NC NC LDQS NC NC NC VDD VDD VDD NC NC NC NC NC LDM /WE /WE /WE /CAS /CAS /CAS /RAS /RAS /RAS /CS /CS /CS NC NC NC BA0 BA0 BA0 BA1 BA1 BA1 A10(AP) A10(AP) A10(AP) A0 A0 A0 A1 A1 A1 A2 A2 A2 A3 A3 A3 VDD VDD VDD Features - Power supply: VDD, VDDQ = 2.5V ± 0.2V - Data Rate: 333Mbps/266Mbps (max.) - Double Data Rate architecture; two data transfers per clock cycle - Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver - Data inputs, outputs, and DM are synchronized with DQS - 4 internal banks for concurrent operation - DQS is edge aligned with data for READs; center aligned with data for WRITEs - Differential clock inputs (CK and /CK) .. - DLL aligns DQ and DQS transitions with CK transitions - mands entered on each positive CK edge; data and data mask referenced to both edges of DQS - Data mask (DM) for write data - Auto precharge option for each burst access - SSTL_2 patible I/O - Programmable burst length (BL): 2, 4, 8 - Programmable /CAS latency (CL): 2, 2.5 - Programmable output driver strength: normal/weak - Refresh cycles: 8192 refresh cycles/64ms  7.8µs maximum average periodic refresh interval - 2 variations of refresh ...