Datasheet4U Logo Datasheet4U.com

EDD5116ADTA-LI - 512M bits DDR SDRAM WTR

Download the EDD5116ADTA-LI datasheet PDF. This datasheet also covers the EDD5108ADTA-LI variant, as both devices belong to the same 512m bits ddr sdram wtr family and are provided as variant models within a single manufacturer datasheet.

Description

The EDD5108AD and the EDD5116AD are 512M bits Double Data Rate (DDR) SDRAM.

Read and write operations are performed at the cross points of the CK and the /CK.

This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture.

Features

  • Power supply: VDD, VDDQ = 2.5V ± 0.2V.
  • Data Rate: 333Mbps/266Mbps (max. ).
  • Double Data Rate architecture; two data transfers per clock cycle.
  • Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver.
  • Data inputs, outputs, and DM are synchronized with DQS.
  • 4 internal banks for concurrent operation.
  • DQS is edge aligned with data for READs; center aligned with data for WRITEs.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (EDD5108ADTA-LI_ElpidaMemory.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number EDD5116ADTA-LI
Manufacturer Elpida Memory
File Size 629.72 KB
Description 512M bits DDR SDRAM WTR
Datasheet download datasheet EDD5116ADTA-LI Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
EDD11 Doppelendtriode TELEFUNKEN

Other Datasheets by Elpida Memory

Part Number Description
EDD5116ADTA-E 512M bits DDR SDRAM
EDD5116ADTA 512M bits DDR SDRAM
EDD5116AFTA 512M bits DDR SDRAM
EDD5116AFTA-5 512M bits DDR SDRAM
EDD5116AGTA 512M bits DDR SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DATA SHEET 512M bits DDR SDRAM WTR (Wide Temperature Range) EDD5108ADTA-LI (64M words × 8 bits) EDD5116ADTA-LI (32M words × 16 bits) Description The EDD5108AD and the EDD5116AD are 512M bits Double Data Rate (DDR) SDRAM. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. Pin Configurations /xxx indicates active low signal.
Datasheet originally released: |