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DATA SHEET
512M bits DDR SDRAM
EDD5108AGTA (64M words × 8 bits) EDD5116AGTA (32M words × 16 bits)
Specifications
• Density: 512M bits • Organization ⎯ 16M words × 8 bits × 4 banks (EDD5108AGTA) ⎯ 8M words × 16 bits × 4 banks (EDD5116AGTA) • Package: 66-pin plastic TSOP (II) ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 2.5V ± 0.2V • Data rate: 400Mbps/333Mbps/266Mbps (max.) • Four internal banks for concurrent operation • Interface: SSTL_2 • Burst lengths (BL): 2, 4, 8 • Burst type (BT): ⎯ Sequential (2, 4, 8) ⎯ Interleave (2, 4, 8) • /CAS Latency (CL): 2, 2.5, 3 • Precharge: auto precharge option for each burst access • Driver strength: normal/weak • Refresh: auto-refresh, self-refresh • Refresh cycles: 8192 cycles/64ms ⎯ Average refresh period: 7.